1. Field of the Invention
This invention relates generally to the fabrication of improved semiconductor devices and more particularly to a method of increasing the effective width of P-type channels connecting N-type source and drain regions of transistor elements separated from other transistor elements in the semiconductor device by field oxide regions and P-type channel stop implants.
2. State of the Art
During field oxidation, P-type channel-stop implants (e.g., boron) in P-type substrates typically experience undesired segregation and oxidation-enhanced diffusion. Specifically, during field oxidation, the P-type channel-stop implant preferentially segregates into the field oxide layer resulting in a reduction in concentration of the implant in the silicon at the field oxide/silicon interface. Also, during field oxidation, the P-type channel-stop implant also diffuses into areas where transistor elements bordering the field oxide regions including the P-type channel connecting the N-type source and drain regions of a transistor element are to be formed.
A reduction in the P-type channel-stop implant concentration at the field oxide/silicon interface enhances the possibility of undesired inversion under the field oxide and, accordingly, it is common practice to effect a second doping of the P-type channel-stop implant to increase the concentration of this implant at this interface. However, relatively high doses of channel-stop implants are needed in order for acceptable field threshold voltages to be achieved. This also implies that the peak of the channel-stop implant must be deep enough that it is not absorbed by the growing field-oxide interface. On the other hand, if the channel-stop doping is too heavy, it will cause high source/drain-to-substrate capacitances and will reduce source/drain-to-substrate pn junction breakdown voltages.
The lateral diffusion of the P-type dopant in the channel-stop implants also causes the P-type dopant to encroach or diffuse into areas where transistor elements are to be formed and which elements are to be segregated from each other on the semiconductor device by field oxide regions and channel-stop implants. Such encroachment includes diffusion into the area where the channel under the gate which connects the N-type source and drain regions of a transistor element is to be formed. Diffusion of the P-type dopant into the edges of these to-be-formed transistor elements contacting the field oxide, including the edges of the channel tinder the gate which connect N-type source and drain regions, will increase the threshold voltage at the channel edges resulting in a threshold voltage (V.sub.The ) higher at these edges as compared to the threshold voltage (V.sub.The ) in the center portions of the channel. As a result, the edges of these channels under the gate will conduct much less current than the interior portions, and the channel element will behave as if it was more narrowly constructed. The effect is also enhanced when the dose of the channel-stop implant is increased.
There have been several attempts to resolve the above-identified problems. For example, it has been reported that the extent of the channel-stop implant diffusion can be reduced by using high pressure oxidation (HIPOX) to grow the field oxide, by using germanium-boron co-implants, or by using chlorine implants. HIPOX allows the oxide-growth temperature to be reduced, which reduces the diffusion length of the implant. The germanium-boron co-implants exploit the fact that boron diffuses with a lower diffusivity in the presence of implanted germanium, and boron segregation effects are also reduced. The chlorine implant is performed in the field regions prior to field oxidation, and this causes the oxide to grow at a faster rate. Consequently, the field oxide can be grown in less time at the same temperature thereby reducing boron diffusion.
Another method is identified in U.S. Pat. No. 4,554,726. In this patent, a photoresist is patterned to expose portions of the substrate for the N-type type tubs. Phosphorus and arsenic are implanted followed by photoresist stripping and oxidation of the N-type tub surface. Boron is then implanted for the P-type tub, and the oxide stripped. A dopant drive-in heating step is then accomplished to drive the dopants deeper into the semiconductor substrate, thereby forming the N-type and P-type tubs. A second boron implant into the P-type tubs is performed. A subsequent lithography step then defines an opening in the masking layer at the boundary between the N-type and P-type tubs. An oxidation step follows, to form the "field oxide" region, which isolates the N-type tubs from the P-type tubs at the surface of the substrate. The second boron implant then forms the "channel stop" region under the field oxide in the P-type tub, which aids in isolating the N-channel devices to be formed therein. In order to retain the second boron implant near the oxide/silicon interface, the field oxide is formed during a relatively brief oxidation process that is accomplished in steam at high pressure.
This problem has also been addressed in U.S. Pat. No. 5,045,898. This patent relates to a CMOS integrated circuit having a P-type region and an N-type region. In particular, this patent implants a boron channel-stop at a depth at least as great as the depth of the field oxide in the silicon substrate. In other words, the boron channel-stop implant has an energy selected so that the boron concentration is just below the subsequently formed field oxide.
However, although the above solutions have achieved a measure of success, additional methods must be employed to inhibit reduction in the effective width of P-type channels connecting N-type source and drain regions of transistor elements in semiconductor devices if further successful miniaturization of integrated circuits is to be achieved.